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1. general description the pca9543a/43b/43c is a bidirectional translating switch, controlled by the i 2 c-bus. the scl/sda upstream pair fans out to two downstream pairs, or channels. any individual scx/sdx channels or combination of channels can be selected, determined by the contents of the programmable control register. two interrupt inputs, int0 and int1, one for each of the downstream pairs, are provided. one interrupt output, int, which acts as an and of the two interrupt inputs, is provided. an active low reset input allows the pca9543x to recover from a situation where one of the downstream i 2 c-buses is stuck in a low state. pulling the reset pin low resets the i 2 c-bus state machine and causes all the channels to be deselected, as does the internal power-on reset function. the pass gates of the switches are constructed such that the v dd pin can be used to limit the maximum high voltage which will be passed by the pca9543x. this allows the use of different bus voltages on each scx/sdx pair, so that 1.8 v, 2.5 v, or 3.3 v parts can communicate with 5 v parts without any additional protection. external pull-up resistors pull the bus up to the desired voltage level for each channel. all i/o pins are 5 v tolerant. the pca9543a, pca9543b and pca9543c are identical except for the ?xed portion of the slave address. 2. features n 1-of-2 bidirectional translating switches n i 2 c-bus interface logic; compatible with smbus standards n 2 active low interrupt inputs n active low interrupt output n active low reset input n 2 address pins allowing up to 4 devices on the i 2 c-bus n alternate address versions a, b and c allow up to a total of 12 devices on the bus for larger systems or to resolve address con?icts n channel selection via i 2 c-bus, in any combination n power-up with all switch channels deselected n low r on switches n allows voltage level translation between 1.8 v, 2.5 v, 3.3 v and 5 v buses n no glitch on power-up n supports hot insertion n low standby current n operating power supply voltage range of 2.3 v to 5.5 v pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset rev. 06 15 june 2009 product data sheet
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 2 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset n 5 v tolerant inputs n 0 hz to 400 khz clock frequency n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma n packages offered: so14, tssop14 3. ordering information 3.1 ordering options table 1. ordering information type number package name description version pca9543ad so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 pca9543apw tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 pca9543bpw pca9543cpw table 2. ordering options type number topside mark temperature range (t amb ) pca9543ad pca9543ad t amb = - 40 c to +85 c pca9543apw pa9543a t amb = - 40 c to +85 c pca9543bpw pa9543b t amb = - 40 c to +85 c pca9543cpw pa9543c t amb = - 40 c to +85 c
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 3 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 4. block diagram fig 1. block diagram of pca9543a/43b/43c switch control logic pca9543a/43b/43c power-on reset 002aab180 sc0 sc1 sd0 sd1 v ss v dd reset i 2 c-bus control input filter scl sda a0 a1 interrupt logic int0 to int1 int
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 4 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 5. pinning information 5.1 pinning 5.2 pin description fig 2. pin con?guration for so14 fig 3. pin con?guration for tssop14 pca9543ad a0 v dd a1 sda reset scl int0 int sd0 sc1 sc0 sd1 v ss int1 002aab178 1 2 3 4 5 6 7 8 10 9 12 11 14 13 v dd sda scl int sc1 sd1 int1 a0 a1 reset int0 sd0 sc0 v ss pca9543apw pca9543bpw pca9543cpw 002aab179 1 2 3 4 5 6 7 8 10 9 12 11 14 13 table 3. pin description symbol pin description a0 1 address input 0 a1 2 address input 1 reset 3 active low reset input int0 4 active low interrupt input 0 sd0 5 serial data 0 sc0 6 serial clock 0 v ss 7 supply ground int1 8 active low interrupt input 1 sd1 9 serial data 1 sc1 10 serial clock 1 int 11 active low interrupt output scl 12 serial clock line sda 13 serial data line v dd 14 supply voltage
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 5 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 6. functional description refer to figure 1 bloc k diag r am of pca9543a/43b/43c . 6.1 device address following a start condition, the bus master must output the address of the slave it is accessing. the address of the pca9543a is shown in figure 4 . to conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled high or low. the last bit of the slave address de?nes the operation to be performed. when set to logic 1 a read is selected, while a logic 0 selects a write operation. the pca9543b and pca9543c are alternate address versions if needed for larger systems or to resolve address con?icts. the data sheet will reference the pca9543a, but the pca9543b and pca9543c function identically except for the slave address. 6.2 control register following the successful acknowledgement of the slave address, the bus master will send a byte to the pca9543a, which will be stored in the control register. if multiple bytes are received by the pca9543a, it will save the last byte received. this register can be written and read via the i 2 c-bus. fig 4. slave address pca9543a fig 5. slave address pca9543b fig 6. slave address pca9543c 002aab169 1 1 1 0 0 a1 a0 r/w fixed hardware selectable 002aab799 1 1 1 1 0 a1 a0 r/w fixed hardware selectable 002aab800 0 1 1 0 0 a1 a0 r/w fixed hardware selectable fig 7. control register 002aab181 x x int 1 int 0 x x b1 b0 channel selection bits (read/write) 76543210 interrupt bits (read only) channel 0 channel 1 int0 int1
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 6 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 6.2.1 control register de?nition one or several scx/sdx downstream pair, or channel, is selected by the contents of the control register. this register is written after the pca9543a has been addressed. the 2 lsbs of the control byte are used to determine which channel is to be selected. when a channel is selected, the channel will become active after a stop condition has been placed on the i 2 c-bus. this ensures that all scx/sdx lines will be in a high state when the channel is made active, so that no false conditions are generated at the time of connection. remark: channel 0 and channel 1 can be enabled at the same time. care should be taken not to exceed the maximum bus capacitance. 6.2.2 interrupt handling the pca9543a provides 2 interrupt inputs, one for each channel, and one open-drain interrupt output. when an interrupt is generated by any device, it will be detected by the pca9543a and the interrupt output will be driven low. the channel need not be active for detection of the interrupt. a bit is also set in the control register. bit 4 and bit 5 of the control register corresponds to the int0 and int1 inputs of the pca9543a, respectively. therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. the master can then address the pca9543a and read the contents of the control register to determine which channel contains the device generating the interrupt. the master can then recon?gure the pca9543a to select this channel, and locate the device generating the interrupt and clear it. it should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. the interrupt inputs may be used as general purpose inputs if the interrupt function is not required. if unused, interrupt input(s) must be connected to v dd through a pull-up resistor. table 4. control register: writechannel selection; readchannel status d7 d6 int1 int0 d3 d2 b1 b0 command xxxxxxx 0 channel 0 disabled 1 channel 0 enabled xxxxxx 0 x channel 1 disabled 1 channel 1 enabled 00000000no channel selected; power-up/reset default state table 5. control register: readinterrupt 7 6 int1 int0 3 2 b1 b0 command xxx 0 xxxx no interrupt on channel 0 1 interrupt on channel 0 xx 0 xxxxx no interrupt on channel 1 1 interrupt on channel 1
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 7 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset remark: two interrupts can be active at the same time. 6.3 reset input the reset input is an active low signal which may be used to recover from a bus fault condition. by asserting this signal low for a minimum of t w(rst)l , the pca9543a will reset its registers and i 2 c-bus state machine and will deselect all channels. the reset input must be connected to v dd through a pull-up resistor. 6.4 power-on reset when power is applied to v dd , an internal power-on reset (por) holds the pca9543a in a reset condition until v dd has reached v por . at this point, the reset condition is released and the pca9543a registers and i 2 c-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. thereafter, v dd must be lowered below 0.2 v to reset the device. 6.5 voltage translation the pass gate transistors of the pca9543a are constructed such that the v dd voltage can be used to limit the maximum voltage that will be passed from one i 2 c-bus to another. figure 8 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data speci?ed in section 10 static char acter istics of this data sheet). in order for the pca9543a to act as a voltage translator, the v o(sw) voltage should be equal to, or lower than the lowest bus voltage. for example, if the main bus was running at 5 v, and the downstream buses were 3.3 v and 2.7 v, then v o(sw) should be equal to or below 2.7 v to effectively clamp the downstream bus voltages. looking at (1) maximum (2) typical (3) minimum fig 8. pass gate voltage versus supply voltage v dd (v) 2.0 5.5 4.5 3.0 4.0 002aaa964 3.0 2.0 4.0 5.0 v o(sw) (v) 1.0 3.5 5.0 2.5 (1) (2) (3)
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 8 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset figure 8 , we see that v o(sw)(max) will be at 2.7 v when the pca9543a supply voltage is 3.5 v or lower, so the pca9543a supply voltage could be set to 3.3 v. pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see figure 15 ). more information can be found in application note an262: pca954x family of i 2 c/smbus multiplexers and switches . 7. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 7.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 9 ). 7.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is de?ned as the start condition (s). a low-to-high transition of the data line while the clock is high is de?ned as the stop condition (p) (see figure 10 ). fig 9. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 10. de?nition of start and stop conditions mba608 sda scl p stop condition s start condition
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 9 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 7.3 system con?guration a device generating a message is a transmitter, a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 11 ). 7.4 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also, a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 11. system con?guration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c-bus multiplexer slave fig 12. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 10 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 7.5 bus transactions data is transmitted to the pca9543a control register using the write mode as shown in figure 13 . data is read from pca9543a using the read mode as shown in figure 14 . fig 13. write control register fig 14. read control register 002aab182 xxxxxxb1b0 1 1 0 0 a1 a0 0 a s 1 a p slave address start condition r/w acknowledge from slave acknowledge from slave control register sda stop condition 002aab183 x x int1 int0 x x b1 b0 1 1 0 0 a1 a0 1 a s 1 na p slave address start condition r/w acknowledge from slave no acknowledge from master control register sda stop condition last byte
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 11 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 8. application design-in information 9. limiting values [1] the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not exceed 125 c. (1) if the device generating the interrupt has an open-drain output structure or can be 3-stated, a pull-up resistor is required. if the device generating the interrupt has a totem pole output structure and cannot be 3-stated, a pull-up resistor is not required. the interrupt inputs should not be left ?oating. fig 15. typical application pca9543a sd0 sc0 a1 a0 v ss sda scl reset v dd = 3.3 v v dd = 2.7 v to 5.5 v i 2 c/smbus master 002aab184 sda scl channel 0 v = 2.7 v to 5.5 v int int0 see note (1) sd1 sc1 channel 1 v = 2.7 v to 5.5 v int1 see note (1) table 6. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to v ss (groun d=0v). [1] symbol parameter conditions min max unit v dd supply voltage - 0.5 +7.0 v v i input voltage - 0.5 +7.0 v i i input current - 20 ma i o output current - 25 ma i dd supply current - 100 ma i ss ground supply current - 100 ma p tot total power dissipation - 400 mw t stg storage temperature - 60 +150 c t amb ambient temperature operating - 40 +85 c
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 12 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 10. static characteristics [1] for operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] v dd must be lowered to 0.2 v in order to reset part. table 7. static characteristics at v dd = 2.3 v to 3.6 v v ss =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. see t ab le 8 on page 13 for v dd = 4.5 v to 5.5 v. [1] symbol parameter conditions min typ max unit supply v dd supply voltage 2.3 - 3.6 v i dd supply current operating mode; v dd = 3.6 v; no load; v i =v dd or v ss ; f scl = 100 khz - 40 100 m a i stb standby current standby mode; v dd = 3.6 v; no load; v i =v dd or v ss ; f scl = 0 khz - 0.2 1 m a v por power-on reset voltage no load; v i =v dd or v ss [2] - 1.6 2.1 v input scl; input/output sda v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -6 v i ol low-level output current v ol = 0.4 v 3 - - ma v ol = 0.6 v 6 - - ma i l leakage current v i =v dd or v ss - 1-+1 m a c i input capacitance v i =v ss - 9 10 pf select inputs a0, a1, int0, int1, reset v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -v dd + 0.5 v i li input leakage current v i =v dd or v ss - 1-+1 m a c i input capacitance v i =v ss - 1.6 3 pf pass gate r on on-state resistance v dd = 3.0 to 3.6 v; v o = 0.4 v; i o =15ma 51130 w v dd = 2.3 v to 2.7 v; v o = 0.4 v; i o =10ma 71655 w v o(sw) switch output voltage v i(sw) =v dd = 3.3 v; i o(sw) = - 100 m a - 1.9 - v v i(sw) =v dd = 3.0 v to 3.6 v; i o(sw) = - 100 m a 1.6 - 2.8 v v i(sw) =v dd = 2.5 v; i o(sw) = - 100 m a - 1.5 - v v i(sw) =v dd = 2.5 v to 2.7 v; i o(sw) = - 100 m a 1.1 - 2.0 v i l leakage current v i =v dd or v ss - 1-+1 m a c io input/output capacitance v i =v ss -35 pf int output i ol low-level output current v ol = 0.4 v 3 - - ma i oh high-level output current - - +100 m a
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 13 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset [1] for operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] v dd must be lowered to 0.2 v in order to reset part. table 8. static characteristics at v dd = 4.5 v to 5.5 v v ss = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. see t ab le 7 on page 12 for v dd = 2.3 v to 3.6 v. [1] symbol parameter conditions min typ max unit supply v dd supply voltage 4.5 - 5.5 v i dd supply current operating mode; v dd = 5.5 v; no load; v i =v dd or v ss ; f scl = 100 khz - 25 100 m a i stb standby current standby mode; v dd = 5.5 v; no load; v i =v dd or v ss ; f scl = 0 khz - 0.2 1 m a v por power-on reset voltage no load; v i =v dd or v ss [2] - 1.7 2.1 v input scl; input/output sda v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -6 v i ol low-level output current v ol = 0.4 v 3 - - ma v ol = 0.6 v 6 - - ma i l leakage current v i =v dd or v ss - 1- +1 m a c i input capacitance v i =v ss - 9 10 pf select inputs a0, a1, int0 to int3, reset v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -v dd + 0.5 v i li input leakage current v i =v dd or v ss - 1 - +50 m a c i input capacitance v i =v ss -25 pf pass gate r on on-state resistance v dd = 4.5 v to 5.5 v; v o = 0.4 v; i o =15ma 4924 w v o(sw) switch output voltage v i(sw) =v dd = 5.0 v; i o(sw) = - 100 m a - 3.6 - v v i(sw) =v dd = 4.5 v to 5.5 v; i o(sw) = - 100 m a 2.6 - 4.5 v i l leakage current v i =v dd or v ss - 1 - +100 m a c io input/output capacitance v i =v ss -35 pf int output i ol low-level output current v ol = 0.4 v 3 - - ma i oh high-level output current - - +100 m a
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 14 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 11. dynamic characteristics [1] pass gate propagation delay is calculated from the 20 w typical r on and the 15 pf load capacitance. [2] hold time (repeated) start condition. after this period, the ?rst clock pulse is generated. [3] a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih(min) of the scl signal) in order to bridge the unde?ned region of the falling edge of scl. [4] c b = total capacitance of one bus line in pf. [5] measurements taken with 1 k w pull-up resistor and 50 pf load. table 9. dynamic characteristics symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max t pd propagation delay from sda to sdx, or scl to scx - 0.3 [1] - 0.3 [1] ns f scl scl clock frequency 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - m s t hd;sta hold time (repeated) start condition [2] 4.0 - 0.6 - m s t low low period of the scl clock 4.7 - 1.3 - m s t high high period of the scl clock 4.0 - 0.6 - m s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - m s t su;sto set-up time for stop condition 4.0 - 0.6 - m s t hd;dat data hold time 0 [3] 3.45 0 [3] 0.9 m s t su;dat data set-up time 250 - 100 - ns t r rise time of both sda and scl signals - 1000 20 + 0.1c b [4] 300 ns t f fall time of both sda and scl signals - 300 20 + 0.1c b [4] 300 ns c b capacitive load for each bus line - 400 - 400 pf t sp pulse width of spikes that must be suppressed by the input ?lter - 50 - 50 ns t vd;dat data valid time high-to-low [5] -1 - 1 m s low-to-high [5] - 0.6 - 0.6 m s t vd;ack data valid acknowledge time - 1 - 1 m s int t v(intnn-intn) valid time from intn to int signal - 4 - 4 m s t d(intnn-intn) delay time from intn to int inactive - 2 - 2 m s t w(rej)l low-level rejection time intn inputs 1 - 1 - m s t w(rej)h high-level rejection time intn inputs 0.5 - 0.5 - m s reset t w(rst)l low-level reset time 4 - 4 - ns t rst reset time sda clear 500 - 500 - ns t rec;sta recovery time to start condition 0 - 0 - ns
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 15 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset fig 16. de?nition of timing on the i 2 c-bus t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 fig 17. de?nition of reset timing sda scl 002aac549 50 % 30 % 50 % 50 % t rec;sta t w(rst)l reset start t rst ack or read cycle rise and fall times refer to v il and v ih . fig 18. i 2 c-bus timing diagram scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 002aab175 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) 1 /f scl t r t vd;dat
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 16 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 12. package outline fig 19. package outline sot108-1 (so14) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 17 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset fig 20. package outline sot402-1 (tssop14) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 18 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 19 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 13.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 21 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 10 and 11 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 21 . table 10. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 11. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 20 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 14. abbreviations msl: moisture sensitivity level fig 21. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 12. abbreviations acronym description cdm charged-device model esd electrostatic discharge hbm human body model ic integrated circuit i 2 c-bus inter-integrated circuit bus lsb least signi?cant bit mm machine model msb most signi?cant bit pcb printed-circuit board smbus system management bus
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 21 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 15. revision history table 13. revision history document id release date data sheet status change notice supersedes pca9543a_43b_43c_6 20090615 product data sheet - pca9543a_43b_43c_5 modi?cations: ? t ab le 9 dynamic char acter istics : C symbol t f : changed unit from m s to ns C symbol c b : changed unit from m s to pf pca9543a_43b_43c_5 20081117 product data sheet - pca9543a_43b_43c_4 pca9543a_43b_43c_4 20061020 product data sheet - pca9543a_3 pca9543a_3 (9397 750 14316) 20050321 product data sheet - pca9543a_2 pca9543a_2 (9397 750 13988) 20040929 objective data sheet - pca9543a_1 pca9543a_1 (9397 750 13299) 20040728 objective data sheet - -
pca9543a_43b_43c_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 15 june 2009 22 of 23 nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 16.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 16.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 17. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors pca9543a/43b/43c 2-channel i 2 c-bus switch with interrupt logic and reset ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 15 june 2009 document identifier: pca9543a_43b_43c_6 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 5 6.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 control register . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2.1 control register de?nition . . . . . . . . . . . . . . . . . 6 6.2.2 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 6 6.3 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.4 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.5 voltage translation . . . . . . . . . . . . . . . . . . . . . . 7 7 characteristics of the i 2 c-bus. . . . . . . . . . . . . . 8 7.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 start and stop conditions . . . . . . . . . . . . . . 8 7.3 system con?guration . . . . . . . . . . . . . . . . . . . . 9 7.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.5 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 10 8 application design-in information . . . . . . . . . 11 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 10 static characteristics. . . . . . . . . . . . . . . . . . . . 12 11 dynamic characteristics . . . . . . . . . . . . . . . . . 14 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 13 soldering of smd packages . . . . . . . . . . . . . . 18 13.1 introduction to soldering . . . . . . . . . . . . . . . . . 18 13.2 wave and re?ow soldering . . . . . . . . . . . . . . . 18 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 13.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 22 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 16.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 16.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 17 contact information. . . . . . . . . . . . . . . . . . . . . 22 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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